Thanks for looking at my questions.  If you know this type of thing,
the questions should be rather simple.  A couple of things though. 
Please explain how you determined the answer as that is what I am
interested in.  Please do not use the exact values in the questions,
you may make up other values.  If a question has a part a and b, you
only need to answer one part if the second part is solved using the
same method.
------------------------------------------------------------------------
 
****Assume that a computer’s address bus is 7 bits wide. 
 
1. How many memory locations can the computer have?  
 
2.If the memory system is byte addressable, how many bytes of memory
can it have?
 
3. How many bytes of memory can the system have if it is exactly
16-bit addressable?
  
 
******For the following questions, refer to figure here
http://www.geocities.com/somoneelse1 and assume byte addressability
(and a 7-bit address bus) (unless stated otherwise).
 
1. What would you assume the size of a word in this system to be? Why?

Hello Linkinpark,

As you have asked, I will describe how to get the answers (a
derivation and answer for an eight bit address bus).

Q1: How many memory locations?

A1: If I had a 1 bit address bus, I can access two memory locations (0
and 1). With a 2 bit address bus, I can access four memory locations
(0, 1, 2, and 3). Adding each bit increases the number of locations by
a factor of two (zero through (2^n)-1). In this way, you can derive
the number of memory locations for 8 bits as 2^8 or locations 0
through 255.

Q2: How many bytes in byte addressable memory?

A2: Each memory location represents a byte, so the number of bytes is
equal to the number of memory locations. (answer to Q1)

Q3: How many bytes if 16 bit addressable?

A3: Hmm. I am not quite sure what is meant by this so I'll answer it a
couple different ways. If you are still using the 7 bit address bus
and 16 bit values, then the answer is ...
  2 bytes / memory location x # of memory locations = total number of
bytes
If you are using 16 bit addresses and byte addressable memory, then
the answer is ...
 1 byte / memory location x (2^16) memory locations
If you mean something else - please use a clarification request to
provide more information.

Q4: (second labeled #1) What is the word size of this system and why?

A4: There is some uncertainty based on the diagram so I'll answer it
both ways and recommend an answer.

Look at the diagram to see two memory banks, eight bits each. Also
note the width of the data at the bottom which has the (/ 16)
notation. That implies 16 bit values are fetched with each memory
reference.  From the data bus size, the "word size" would be 2 x 8 =
16.

However, only six bits of the seven bit address are used to access the
memory banks. There are 2^7 total bytes (two 2^6 byte banks) which
would imply 8 bit memory locations with a two location fetch in each
memory cycle. That implies 1 x 8 = 8 bit word size.

You could make the argument either way, but I would expect the latter
(8 bit) to be "correct".

If you are interested, there are also a number of good sites available
that describe the design of memory systems. Let me know if you are
interested in further information like that or if the answers above
are unclear.

  --Maniac