I need some help with the following question:

The instruction format for a certain architecture consists of on
operation field (Op Code) and two operand fields; the first operand is
always a register address and the second operand is always a memory
address. If the size of the Op Code field is 9 bits, the size of the
Register operand field is 3 bits, the architecture supports a memory
size of 8 GB, and the memory word size is 64 bits answer the following
questions:

1.  What is the maximum number of operations supported by this
architecture?
2.  How many General Purpose Registers are implied in this
architecture?
3.  What is the total size, in bits, of an instruction? 
4.  How many words are there in a fully configured memory system? 
5.  What is the minimum address size, in bits, needed to address any
word (not byte) in memory?

If the opcode field is 9 bits in length, then there are 2^9 = 512
possible instructions.

If the register field is 3 bits in length, thene there are at most 8
possible general purpose registers.

If the word size is 64bits and the total memory capacity is 8GB then
there are 1G addresses (1G x 64b = 1G x 8B), meaning a 30-bit address
field (2^30=1G).  (If each byte is individually addressable then there
would need to be 3 additional bits in the address field; 2^3=8.)

Thus the total number of bits per instruction, assuming a flat memory
model, is between 9+3+30=42 and 9+3+33=45 bits.