i'm doing a project using agilent design software (ADS) designing a
w/lan transceiver operating at 25GHz and with a bandwidth of 250MHz.
The project is to investigate the applicability of the AMS  S35 HBT
BiCMOS  process in developing circuits for the next generation of
wireless links operating at 25GHz. i need a working design and
simulation results that enabled the design to be completed - it has to
be done in ADS (agilent design software). any ideas? i need a complete
example. i'm out of ideas and desperate..

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Clarification of Question by blondnspikey-ga on 19 Apr 2004 06:06 PDT

ok. its at transistor level design, i.e, draw out schematics and
simulate them basically fine tuning the design. preferably using bjt's
for the amplifier and probably mosfets for the mixer etc...

It's not clear what level the design needs to be at (transistor or
functional block). Do you want OFDM, DSSS or both? I'd guess OFDM is
more interesting, especially if you're worried about VCO phase noise.
There is a WLAN design guide that goes with ADS. Simply increasing the
clock speed for the modulation is an easy way to increase the
bandwidth

ok. its at transistor level design, i.e, draw out schematics and
simulate them basically fine tuning the design. preferably using bjt's
for the amplifier and probably mosfets for the mixer etc...

It is still not very clear about what you are looking for.  Just a low
noise amplifier followed by a mixer?  I notice that you don't have any
specifications listed (i.e. noise figure, power, gain, die wire-bonded
to ceramic substrate?, differential output, z0=50ohms, etc.), so I'm
assuming that this is for some sort of school project, not an actual
design you are going to tape out. If that is the case, then you'll
probably be able to get something past your professor using this
process.  Otherwise I don't think you'll find the transistors fast
enough (ft=50GHz) to get enough gain at 25GHz in a single stage. And
if you try multiple stages, you'll probably have too much noise. I'd
recommend taking a look at a faster process, like IBM's SiGe 7HP
(120Ghz ft).  If you are just doing the LNA/mixer, I'd guess you'll
end up with about 25 (bipolar) transistors (including bias) with no
CMOS and your die will be pad limited. If you decide to go with an
expert, I think you could get a pretty good feasibility study for
about $20,000 dollars, charged out at $150 per hour.

Even 20,000 is still not enough.I am sure no expert can finish in one
month for the first time.