Google Answers: Asynchronous State Machines (Logic Design)

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Q: Asynchronous State Machines (Logic Design) ( No Answer, 0 Comments )

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Subject: Asynchronous State Machines (Logic Design)
Category: Science > Technology
Asked by: mr_p_kniss-ga
List Price: $50.00

Posted: 18 Jun 2004 12:55 PDT
Expires: 18 Jul 2004 12:55 PDT
Question ID: 363096

A state machine has one input and two outputs Q1 and Q2. Normally
Q1Q2=00. If the input sequence X=0110 is detected, then Q1Q2=01 for
one clock period before returning to Q1Q2=00. If the input sequence
X=1011 is detected then Q1Q2=01 for one clock period before returning
to Q1Q2=00.

Given that the least significant bit of the input sequence must arrive
first, produce a Moore ASM chart which describes the operation of this
state macnine.

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