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Q: verilog lsfr (linear shift feed back register) ( No Answer,   2 Comments )
Question  
Subject: verilog lsfr (linear shift feed back register)
Category: Computers > Programming
Asked by: motts786-ga
List Price: $20.00
Posted: 06 May 2005 16:45 PDT
Expires: 07 May 2005 17:05 PDT
Question ID: 518693
I need help with coding a lsfr in Verilog. As soon as i get a reply i
will post the full specs.

Clarification of Question by motts786-ga on 06 May 2005 22:51 PDT
Sorry let me re-phrase, I meant I need strucural code in verilog for a
LSFR (linear shift feed-back register). Specs will be posted when
requested.
Thank You

Clarification of Question by motts786-ga on 07 May 2005 16:48 PDT
The module for the 9-stage LFSR discussed above has the following module
definition:
module LFSR_UDP (q, IC, Tap_c, Start, Clock);
    output [9:1] q; // q[9] corresponds to stage 9.
    input [9:1] IC; // IC[9] corresponds to stage 9.
    input [2:0] Tap_c; // Tap_c = 0, 1, 2, etc. for feedback of stage 1, 2, 3, etc.
    input Start; // If Start = 1, the LFSR takes the value IC.
    input Clock; // LFSR shifts on positive edge of Clock.

The value of Tap_c identifies the stages that supply inputs to the XOR
block as specified
in the following table.

This assignment deals with design and testing a structural-level Verilog model of
a 9-stage linear-feedback shift register (LFSR). The LFSR incorporates
edge-triggered D
flip flops that have preset and clear inputs for loading an arbitrary
initial state. The D flip
flop is implemented as a user-defined primitive (UDP).
The figure below illustrates the feedback mechanism of the LFSR designed in this
assignment. Stages are numbered 1 through 9. The output stage (stage
9) and one other
stage feed back through an XOR gate to the D input of stage 1; we
exclude more general
cases in which feedback from more than two stages is permitted. In the
general case, the
bit positions selected for use in the feedback function are called
taps. The list of the taps
is known as the tap sequence. In this assignment the tap sequence
consists of stage 9 and
one other stage. The Tap Coefficient is a 3-bit vector that identifies
the stage (i.e., one of
the stages numbered 1 through 8) whose output is combined with the
output of stage 9 in
the XOR gate that drives the D input of stage 1.


A sequence refers to the successive 9-bit values contained in an LFSR after each
shift operation when the LFSR is subjected to repeated one-place shift
operations. The
period of a sequence is the number of different values that appear in
the sequence before
values begin to repeat. All LFSRs have a sequence that contains only
the value 0; an
LFSR that contains the value 0 will remain in that state forever
unless a different value is
forced into the LFSR. Depending on the tap sequence, an LFSR has two or more
sequences. A 9-stage LFSR is said to have a maximal-length sequence
(with a period of
511) if it has only one sequence other than the 0 sequence. The tap
sequence (9, 5) is
known to produce a maximal-length sequence when the 9-stage LFSR is
initialized to a
value other than 0. Other tap sequences may produce multiple
sequences; in this case, the
value in the LFSR determines in which sequence the LFSR is operating at any given
time.
Answer  
There is no answer at this time.

Comments  
Subject: Re: verilog lsfr (linear shift feed back register)
From: bozo99-ga on 06 May 2005 19:01 PDT
 
I'd start with a short one and run it to completion.
Subject: Re: verilog lsfr (linear shift feed back register)
From: motts786-ga on 07 May 2005 16:51 PDT
 
Please help, I'm short on time. Thank you for viewing.

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