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Q: VERILOG linear feedback shift register ( Answered ,   3 Comments )
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 Subject: VERILOG linear feedback shift register Category: Computers > Programming Asked by: motts786-ga List Price: \$50.00 Posted: 07 May 2005 17:10 PDT Expires: 06 Jun 2005 17:10 PDT Question ID: 519017
 ```I need Verilog structural code for lfsr(linear feedback shift register). The module for the 9-stage LFSR discussed above has the following module definition: module LFSR_UDP (q, IC, Tap_c, Start, Clock); output [9:1] q; // q[9] corresponds to stage 9. input [9:1] IC; // IC[9] corresponds to stage 9. input [2:0] Tap_c; // Tap_c = 0, 1, 2, etc. for feedback of stage 1, 2, 3, etc. input Start; // If Start = 1, the LFSR takes the value IC. input Clock; // LFSR shifts on positive edge of Clock. The value of Tap_c identifies the stages that supply inputs to the XOR block as specified in the following table. This assignment deals with design and testing a structural-level Verilog model of a 9-stage linear-feedback shift register (LFSR). The LFSR incorporates edge-triggered D flip flops that have preset and clear inputs for loading an arbitrary initial state. The D flip flop is implemented as a user-defined primitive (UDP). The figure below illustrates the feedback mechanism of the LFSR designed in this assignment. Stages are numbered 1 through 9. The output stage (stage 9) and one other stage feed back through an XOR gate to the D input of stage 1; we exclude more general cases in which feedback from more than two stages is permitted. In the general case, the bit positions selected for use in the feedback function are called taps. The list of the taps is known as the tap sequence. In this assignment the tap sequence consists of stage 9 and one other stage. The Tap Coefficient is a 3-bit vector that identifies the stage (i.e., one of the stages numbered 1 through 8) whose output is combined with the output of stage 9 in the XOR gate that drives the D input of stage 1. A sequence refers to the successive 9-bit values contained in an LFSR after each shift operation when the LFSR is subjected to repeated one-place shift operations. The period of a sequence is the number of different values that appear in the sequence before values begin to repeat. All LFSRs have a sequence that contains only the value 0; an LFSR that contains the value 0 will remain in that state forever unless a different value is forced into the LFSR. Depending on the tap sequence, an LFSR has two or more sequences. A 9-stage LFSR is said to have a maximal-length sequence (with a period of 511) if it has only one sequence other than the 0 sequence. The tap sequence (9, 5) is known to produce a maximal-length sequence when the 9-stage LFSR is initialized to a value other than 0. Other tap sequences may produce multiple sequences; in this case, the value in the LFSR determines in which sequence the LFSR is operating at any given time.``` Clarification of Question by motts786-ga on 07 May 2005 17:14 PDT `I need this done by MAY 10, 2005 at the LATEST. Please help`
 Subject: Re: VERILOG linear feedback shift register Answered By: studboy-ga on 07 May 2005 20:01 PDT Rated:
 ```OK, I'm going to post two versions--one structural where I assume you have a dff already in your library (I provide a dff model just for reference), and one "implied" structural (this is known as RTL (register transfer level) structural and this is what we used in the industry). Anyway I think you know exactly what I meant when I post it. I recommend tapping node 4 (ie, Tap_c = 4) to produce the LFSR sequence. (PS I will work on your booth mul tomorrow) ----- module dff (Q, D, Clock); output Q; input D; input Clock; reg Q; always @(posedge Clock) begin Q <= D; end endmodule module LFSR_UDP (q, IC, Tap_c, Start, Clock); output [9:1] q; // q[9] corresponds to stage 9. input [9:1] IC; // IC[9] corresponds to stage 9. input [2:0] Tap_c; // Tap_c = 0, 1, 2, etc. for feedback of stage 1, 2, 3, etc. input Start; // If Start = 1, the LFSR takes the value IC. input Clock; // LFSR shifts on positive edge of Clock. wire [9:1] LFSR; dff dff1 (LFSR[1], Start ? IC[1] : LFSR[Tap_c] ^ LFSR[9], Clock); dff dff2 (LFSR[2], Start ? IC[2] : LFSR[1], Clock); dff dff3 (LFSR[3], Start ? IC[3] : LFSR[2], Clock); dff dff4 (LFSR[4], Start ? IC[4] : LFSR[3], Clock); dff dff5 (LFSR[5], Start ? IC[5] : LFSR[4], Clock); dff dff6 (LFSR[6], Start ? IC[6] : LFSR[5], Clock); dff dff7 (LFSR[7], Start ? IC[7] : LFSR[6], Clock); dff dff8 (LFSR[8], Start ? IC[8] : LFSR[7], Clock); dff dff9 (LFSR[9], Start ? IC[9] : LFSR[8], Clock); assign q = LFSR; endmodule module LFSR_implied_structural_RTL (q, IC, Tap_c, Start, Clock); output [9:1] q; // q[9] corresponds to stage 9. input [9:1] IC; // IC[9] corresponds to stage 9. input [2:0] Tap_c; // Tap_c = 0, 1, 2, etc. for feedback of stage 1, 2, 3, etc. input Start; // If Start = 1, the LFSR takes the value IC. input Clock; // LFSR shifts on positive edge of Clock. reg [9:1] LFSR; always @(posedge Clock) begin if (Start) begin LFSR <= IC; end LFSR[1] <= LFSR[Tap_c] ^ LFSR[9]; LFSR[9:2] <= LFSR[8:1]; end assign q = LFSR; endmodule``` Request for Answer Clarification by motts786-ga on 07 May 2005 22:51 PDT ```Not a clarification, but i was wondering if maybe you can post 2 seperate testbenches for the 2 lfsr's that you posted as well. If you want I can pay for the test benches as well, by posting a whole new question for just the test benches. Also I am posting a link for the other question I posted (multiplier) The link has the following: - description (pdf) - test bench - timing diagram LINK: http://www.geocities.com/kevin_bacon1997/ It would be helpful if you could do two versions of the multiplier also just as you did for this one. And again I could post another separate question if you would like me to pay for a second version of the multiplier. Thank You``` Clarification of Answer by studboy-ga on 07 May 2005 23:08 PDT ```No problem. I can come up with the TBs in a couple of days. It's best if you post it as a separate question. Also, I cannot access your link-- http://www.geocities.com/kevin_bacon1997/ When I went there and click on one of the 3 links, it says file not found-- can you make sure you can access the links/check the links? Thanks.``` Clarification of Answer by studboy-ga on 07 May 2005 23:10 PDT ```The advantage of posting it as a separate question is that just in case I ran into some emergencies and cannot get the thing done in time, some other researchers can answer it for you. Other researchers cannot post answers to this same question. Thanks.``` Clarification of Answer by studboy-ga on 07 May 2005 23:38 PDT ```I enhanced the implied_structural_RTL version to a more robust one below: module LFSR_implied_structural_RTL (q, IC, Tap_c, Start, Clock); output [9:1] q; // q[9] corresponds to stage 9. input [9:1] IC; // IC[9] corresponds to stage 9. input [2:0] Tap_c; // Tap_c = 0, 1, 2, etc. for feedback of stage 1, 2, 3, etc. input Start; // If Start = 1, the LFSR takes the value IC. input Clock; // LFSR shifts on positive edge of Clock. reg [9:1] LFSR; always @(posedge Clock) begin if (Start) begin LFSR <= IC; end else begin LFSR[1] <= LFSR[Tap_c] ^ LFSR[9]; LFSR[9:2] <= LFSR[8:1]; end end assign q = LFSR; endmodule``` Clarification of Answer by studboy-ga on 08 May 2005 01:41 PDT ```Please see the testbench I posted for the multiplier-- replace clk with Clock, replace start with Start, replace ab with q, replace a with IC, replace b with Tap_c, and you have yourself a testbench for the LFSR.``` Clarification of Answer by studboy-ga on 08 May 2005 08:56 PDT ```In case you still need it... module testbench; reg clk, start; reg [9:1] ic; reg [2:0] tap_c; wire [9:1] q; LFSR_implied_structural_RTL lfsr1(q, ic, tap_c, start, clk); initial begin clk = 0; \$display("first example: ic = 111111111 tap_c = 4"); ic = 9'b111111111; tap_c = 4; start = 1; #50 start = 0; #5160 \$display("first example done"); \$finish; end always #5 clk = !clk; always @(posedge clk) \$strobe("q: %b", q); endmodule``` Clarification of Answer by studboy-ga on 08 May 2005 08:58 PDT ```If you like, you may pay me extra for the testbench since we take care of them in the same question.``` Clarification of Answer by studboy-ga on 08 May 2005 09:18 PDT ```BTW, you might want to check if the authories really want: LFSR[1] <= LFSR[Tap_c+1] ^ LFSR[9]; Since Tap_c is 3 bits it goes from 0-7, they probably meant for it to go from 1-8.``` Request for Answer Clarification by motts786-ga on 08 May 2005 11:07 PDT ```In the description it says the following: The Tap Coefficient is a 3-bit vector that identifies the stage (i.e., one of the stages numbered 1 through 8) whose output is combined with the output of stage 9 in the XOR gate that drives the D input of stage 1.``` Clarification of Answer by studboy-ga on 08 May 2005 12:10 PDT ```Yes, that's exactly what I meant. The authorities who wrote that description has no clue what they are talking about--3 bits is: 000 to 111-- which is 0 to 7, how could it be 1 to 8? They probably eithe rmeant 4 bits [3:0], or they meant for us to add 1, like I did in: LFSR[1] <= LFSR[Tap_c+1] ^ LFSR[9];``` Request for Answer Clarification by motts786-ga on 08 May 2005 14:24 PDT `I will ask immediately and post asap regarding this. Thank you` Clarification of Answer by studboy-ga on 08 May 2005 15:07 PDT `Thanks!` Request for Answer Clarification by motts786-ga on 09 May 2005 23:48 PDT ```Studboy, I closed the multiplier thread so cant post there anymore. What you instructed me to do worked perfectly. I will just test the lfsr and please let me know about the shifter lab. I can post a working model for you and maybe you could work with that to modify it.``` Request for Answer Clarification by motts786-ga on 10 May 2005 18:26 PDT ```I was wondering if you can help me with the testbench I had to write with this program, It is supposed to display the sequence, the period and tap of that sequence, for all tap values 0-7. And everytime the sequence starts with 1.``` Request for Answer Clarification by motts786-ga on 10 May 2005 18:37 PDT ```I can post what I did so far for the test bench. It does it for the first tap only then it increments the tap and then never changes q again. haha``` Clarification of Answer by studboy-ga on 10 May 2005 19:12 PDT ```shifter lab is already done (behavioral code)--please check your email. lfsr testbench is already posted above. if you want your own, you're welcomed to post it. q is an output, you're supposed to view it, not change it.``` Request for Answer Clarification by motts786-ga on 10 May 2005 19:20 PDT ```what i meant was reset q not change it. When the tap goes from 0 to 1 the sequence 'q' should reset to 1 again and then display q for that tap then repeat the same for tap 2 and so on until tap 7 so you can view all the sequences and the periods for those sequences. Thats what i meant, sorry i wasnt clear the first time``` Clarification of Answer by studboy-ga on 10 May 2005 20:05 PDT ```When tap goes from 0-1, did you "pulse" the start signal? You need to pulse it for a couple of clks (view the waveform). If you want to pulse it for less than one clk, you need to do: always @(posedge Clock or Start) inside lfsr.v (implied structural version)``` Request for Answer Clarification by motts786-ga on 11 May 2005 00:16 PDT ```This is what i did, It seems to give the correct results but I want it to reload the IC when the tap changes. Dont know how to pulse start there. I'm just trying this and that. module testbench; reg clk, start; reg [9:1] ic; reg [2:0] tap_c; //reg flag; wire [9:1] q; reg [15:0] Period; //Integer flag; reg [3:0] count; LFSR_UDP lfsr1(q, ic, tap_c, start, clk); initial begin clk = 0; \$display("Display All Sequence for tap[0-7]: ic = 000000001"); ic = 9'b000000001; tap_c = 0; count=0; start = 1; #13 start = 0;Period = 16'b0000000000000000; end always #5 clk = !clk; always @(posedge clk) begin #10 if (~start) begin Period = Period +1; end \$display("q: %8b Tap Value:%2d ", q, tap_c); end always @(negedge clk) begin if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; tap_c = tap_c +1; count = count +1; if(count == 8)begin \$stop; end end start = 0; Period = 0; end end endmodule``` Clarification of Answer by studboy-ga on 11 May 2005 00:27 PDT ```Just add one line--don't waste time on the testbench: always @(negedge clk) begin if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; #10 start = 0; <---------------- add this tap_c = tap_c +1; count = count +1; if(count == 8)begin \$stop; end end start = 0; Period = 0; end end``` Clarification of Answer by studboy-ga on 11 May 2005 00:28 PDT ```Put it after the tap: always @(negedge clk) begin if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; tap_c = tap_c +1; #10 start = 0; <---------------- add this count = count +1; if(count == 8)begin \$stop; end end start = 0; Period = 0; end end``` Request for Answer Clarification by motts786-ga on 11 May 2005 00:35 PDT `Let me try that. I'm losing my mind!!!` Clarification of Answer by studboy-ga on 11 May 2005 00:37 PDT ```always @(negedge clk) begin if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; tap_c = tap_c +1; #10 start = 0; <---------------- add this count = count +1; if(count == 8)begin \$stop; end end //start = 0; <----------------- no need for this one Period = 0; <----------------- why do you want to set it to 0 here? end end``` Clarification of Answer by studboy-ga on 11 May 2005 00:38 PDT ```always @(negedge clk) begin if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; tap_c = tap_c +1; #10 start = 0; <---------------- add this Period = 0; count = count +1; if(count == 8)begin \$stop; end end //start = 0; //Period = 0; end end``` Request for Answer Clarification by motts786-ga on 11 May 2005 00:48 PDT ```I have to waste time on the testbench, it is part of the requirements. Then i have to use the results from the testbench to write another testbench haha. THis is how it goes: run the first testbench with ic = 1, for all taps 0-7 find the tap with the shortest sequence(period) then the next test bench uses this tap to examine all ic values from ic = 9'b000000001 to ic = 9'b111111111 and see which IC produces the shortest sequence(which has at least a period of 2).``` Clarification of Answer by studboy-ga on 11 May 2005 00:52 PDT `ok` Request for Answer Clarification by motts786-ga on 11 May 2005 00:56 PDT ```always @(negedge clk) begin if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; tap_c = tap_c +1; #10 start = 0; Period = 0; count = count +1; if(count == 8)begin \$stop; end end #1start = 0; <--------I added this and now its pulsing(just like you said) //Period = 0; end end``` Clarification of Answer by studboy-ga on 11 May 2005 01:06 PDT `so it works fine now?` Clarification of Answer by studboy-ga on 11 May 2005 01:12 PDT ```Make sure you're using the latest lfsr.v: module LFSR_implied_structural_RTL (q, IC, Tap_c, Start, Clock); output [9:1] q; // q[9] corresponds to stage 9. input [9:1] IC; // IC[9] corresponds to stage 9. input [2:0] Tap_c; // Tap_c = 0, 1, 2, etc. for feedback of stage 1, 2, 3, etc. input Start; // If Start = 1, the LFSR takes the value IC. input Clock; // LFSR shifts on positive edge of Clock. reg [9:1] LFSR; always @(posedge Clock or Start) begin if (Start) begin LFSR <= IC; end else begin LFSR[1] <= LFSR[Tap_c+1] ^ LFSR[9]; LFSR[9:2] <= LFSR[8:1]; end end assign q = LFSR; endmodule``` Request for Answer Clarification by motts786-ga on 11 May 2005 02:05 PDT ```i'm not using the verion of the lfsr that you just posted. I am using the structural verion, not the implied structural version. The reason is that the instructor specified to use a UDP(the D-FlipFlop).``` Clarification of Answer by studboy-ga on 11 May 2005 02:14 PDT ```Fine. Then model your dff correctly, use a big start pulse (do #10, not #1 STart = 0), and be sure to use the +1. module LFSR_UDP (q, IC, Tap_c, Start, Clock); output [9:1] q; // q[9] corresponds to stage 9. input [9:1] IC; // IC[9] corresponds to stage 9. input [2:0] Tap_c; // Tap_c = 0, 1, 2, etc. for feedback of stage 1, 2, 3, etc. input Start; // If Start = 1, the LFSR takes the value IC. input Clock; // LFSR shifts on positive edge of Clock. wire [9:1] LFSR; dff dff1 (LFSR[1], Start ? IC[1] : LFSR[Tap_c+1] ^ LFSR[9], Clock); <----- dff dff2 (LFSR[2], Start ? IC[2] : LFSR[1], Clock); dff dff3 (LFSR[3], Start ? IC[3] : LFSR[2], Clock); dff dff4 (LFSR[4], Start ? IC[4] : LFSR[3], Clock); dff dff5 (LFSR[5], Start ? IC[5] : LFSR[4], Clock); dff dff6 (LFSR[6], Start ? IC[6] : LFSR[5], Clock); dff dff7 (LFSR[7], Start ? IC[7] : LFSR[6], Clock); dff dff8 (LFSR[8], Start ? IC[8] : LFSR[7], Clock); dff dff9 (LFSR[9], Start ? IC[9] : LFSR[8], Clock); assign q = LFSR; endmodule``` Clarification of Answer by studboy-ga on 11 May 2005 02:19 PDT ```If your instructor insists on a tiny Start pulse, use a different dff (one with an enable) (then tell him he doesn't know what design is all about)``` Request for Answer Clarification by motts786-ga on 11 May 2005 02:28 PDT ```Haha, Thank You! I did use the +1, also i'm trying with #10 right now but for some reason its not working correctly.``` Clarification of Answer by studboy-ga on 11 May 2005 02:29 PDT `Please debug it with a waveform. Do not guess what happens.` Request for Answer Clarification by motts786-ga on 11 May 2005 02:44 PDT ```i'm thinking something along these lines: (I chose 512 for the stop since IC max value is 511) always @(negedge clk) begin if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; //ic = ic +1; #10 start = 0; ic = ic +1; count = count +1; if(count == 512)begin \$stop; end end #5 start = 0; //Period = 0; end``` Clarification of Answer by studboy-ga on 11 May 2005 02:54 PDT ```First of all, the thinking is incorrect: 1) What would you value of ic end up with? ic = ic + 1 after 512, your ic will be 513, is that what you want? Your original count of 8 is correct. 2) Your # numbers are incorrect, have you look at the waveform? This is what you want: IC 1 1 _ _ start _| |__________________________________| |______________ LFSR out 1 ............................. 1...... If you are not seeing that, your testbench is wrong. Think about it. 3) Finally, and most importantly, get some sleep first and look at it in the morning. Your mind needs rest to think correctly.``` Clarification of Answer by studboy-ga on 11 May 2005 02:59 PDT `I was referring to tap_c, -- the ic = 512 case is for your second testbench.` Clarification of Answer by studboy-ga on 11 May 2005 03:07 PDT ```Testbench 1: Fixed IC, loop tap_c from 0-7 Testbench 2: Fixed tap_c, loop IC from 0-511 Do not mix the two testbench into 1.``` Request for Answer Clarification by motts786-ga on 11 May 2005 03:08 PDT ```Sorry, I was referring to the second testbench. The first test bench is now displaying the correct results. I am working on the second test bench. That is why I replaced the count to coincide with the IC. count is now declared as follows: reg [9:0] count; so count is 10 bits reasoning: IC is 9 bits so max val for ic is 511 or 9'b111111111 so we want to stop at IC = 512, since its not possible to rep 512 with 9 bits, I use count to count in parallel with IC's increments. when count is equal to 512 IC will reset to 000000001 and that is where the \$stop statement halts the execution. what do you suggest?``` Clarification of Answer by studboy-ga on 11 May 2005 03:20 PDT ```OK, I see. I thought you were still on the first bench. IC is only 8 bits : [9:1] 0 - 255``` Clarification of Answer by studboy-ga on 11 May 2005 03:25 PDT `Sorry you were right : 9 bits 512 is correct.` Request for Answer Clarification by motts786-ga on 11 May 2005 03:28 PDT `Yeah thanks, There seems to be a problem with the timing.` Clarification of Answer by studboy-ga on 11 May 2005 03:29 PDT ```Also you cannot loop like that--the ic+1 has to be an outer loop--other wise you are changing ic in the middle of the LFSR sequence...``` Request for Answer Clarification by motts786-ga on 11 May 2005 03:29 PDT `I think the problem is the timing for when ic is incremented. Cant figure it out` Clarification of Answer by studboy-ga on 11 May 2005 03:42 PDT ```OK, figure out when end_of_sequence is: if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; if (end_of_each_sequence) ic = ic +1; #10 start = 0; count = count +1; if(ic == 512)begin \$stop; end end #5 start = 0; //Period = 0; end``` Request for Answer Clarification by motts786-ga on 11 May 2005 03:47 PDT ```Thank you so much for your patience, I am confused as to how to use that end_of _sequence bit you just posted.``` Clarification of Answer by studboy-ga on 11 May 2005 03:47 PDT ```How about some variation of this: if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; ic = ic +1; #10 start = 0; count = count +1; if(ic == 512)begin \$stop; end end #5 start = 0; //Period = 0; end``` Clarification of Answer by studboy-ga on 11 May 2005 03:49 PDT ```No need for count if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; if (end_of_each_sequence) ic = ic +1; #10 start = 0; if(ic == 512)begin \$stop; end end #5 start = 0; //Period = 0; end``` Clarification of Answer by studboy-ga on 11 May 2005 03:50 PDT ```if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; ic = ic +1; #10 start = 0; if(ic == 512)begin \$stop; end end #5 start = 0; //Period = 0; end``` Request for Answer Clarification by motts786-ga on 11 May 2005 03:51 PDT ```also in the output it seems as though it is using a previous state to start the next sequence: q: 000000010 Tap Value: 2 q: 000000011 Tap Value: 2 q: 000000110 Tap Value: 2 q: 000001101 Tap Value: 2 q: 000011011 Tap Value: 2 q: 000110110 Tap Value: 2 q: 001101101 Tap Value: 2 q: 011011011 Tap Value: 2 q: 110110110 Tap Value: 2 q: 101101100 Tap Value: 2 q: 011011000 Tap Value: 2 q: 110110000 Tap Value: 2 q: 101100001 Tap Value: 2 q: 011000011 Tap Value: 2 q: 110000110 Tap Value: 2 q: 100001100 Tap Value: 2 q: 000011000 Tap Value: 2 q: 000110000 Tap Value: 2 q: 001100000 Tap Value: 2 q: 011000000 Tap Value: 2 q: 110000000 Tap Value: 2 q: 100000001 Tap Value: 2 Count: 21 q: 000000011 Tap Value: 2 q: 000000100 Tap Value: 2 q: 000001001 Tap Value: 2 q: 000010010 Tap Value: 2 q: 000100100 Tap Value: 2 q: 001001001 Tap Value: 2 q: 010010010 Tap Value: 2 q: 100100100 Tap Value: 2 q: 001001000 Tap Value: 2 q: 010010000 Tap Value: 2 q: 100100000 Tap Value: 2 q: 001000001 Tap Value: 2 q: 010000010 Tap Value: 2 q: 100000100 Tap Value: 2 q: 000001000 Tap Value: 2 q: 000010000 Tap Value: 2 q: 000100000 Tap Value: 2 q: 001000000 Tap Value: 2 q: 010000000 Tap Value: 2 q: 100000000 Tap Value: 2 q: 000000001 Tap Value: 2 q: 000000010 Tap Value: 2 Count: 21``` Request for Answer Clarification by motts786-ga on 11 May 2005 03:53 PDT ```About not using count, ic can only go up to 511 since its only 9 bits. thats why i used count and extended it by one more bit so i can represent 512``` Clarification of Answer by studboy-ga on 11 May 2005 03:55 PDT ```Because that's how your testbench works-- q==ic is your ending condition. Check the waveform``` Clarification of Answer by studboy-ga on 11 May 2005 03:57 PDT ```Hey I need to go. I'm sure you are getting very close. Just check the waveform. The waveform is key to everything. Don't worry about the deadline--get some sleep.``` Request for Answer Clarification by motts786-ga on 11 May 2005 03:58 PDT `Thank you VERY much for your patience` Clarification of Answer by studboy-ga on 11 May 2005 03:59 PDT ```OK, then use the count: if(q==ic)begin if (~start) begin \$display("Count: %2d", Period); Period = 0; start = 1; ic = ic +1; #10 start = 0; count = count +1; if(count == 512)begin \$stop; end end #5 start = 0; //Period = 0; end``` Request for Answer Clarification by motts786-ga on 11 May 2005 05:19 PDT `Will try let me see if this post works` Clarification of Answer by studboy-ga on 11 May 2005 15:13 PDT `Testing.`
 motts786-ga rated this answer: ```Very patient and always ready to help, replied almost as if we were discussing it real-time face to face. Thanks studyboy for the unmatched response time.```

 ```try start off with a 0 or even -1 in the initial block: \$display("Display All Sequence for tap[0-7]: ic = 000000001"); ic = 9'b000000000; tap_c = 0; count=0; start = 1; #13 start = 0;Period = 16'b0000000000000000;```
 ```I cannot post to the clarify answer section anymore--looks like Google Answers ran out of space buffer.```
 `It works for you but it doesn't work for me. I will respond through comments.`