module shifter (result, value_in, direction, type, length);
output [7:0] result;
input [7:0] value_in;
input direction;
input [1:0] type;
input [2:0] length;
reg [7:0] value_out;
always @(value_in or direction or type or length)
begin
case ({direction, type})
3'b0_00: value_out = value_in >> length;
3'b0_01: case(length)
3'b000: value_out = value_in;
3'b001: value_out = {value_in[7], value_in[7:1]};
3'b010: value_out = {{2{value_in[7]}}, value_in[7:2]};
3'b011: value_out = {{3{value_in[7]}}, value_in[7:3]};
3'b100: value_out = {{4{value_in[7]}}, value_in[7:4]};
3'b101: value_out = {{5{value_in[7]}}, value_in[7:5]};
3'b110: value_out = {{6{value_in[7]}}, value_in[7:6]};
3'b111: value_out = {{7{value_in[7]}}, value_in[7]};
endcase
3'b0_10: case(length)
3'b000: value_out = value_in;
3'b001: value_out = {value_in[0], value_in[7:1]};
3'b010: value_out = {value_in[1:0], value_in[7:2]};
3'b011: value_out = {value_in[2:0], value_in[7:3]};
3'b100: value_out = {value_in[3:0], value_in[7:4]};
3'b101: value_out = {value_in[4:0], value_in[7:5]};
3'b110: value_out = {value_in[5:0], value_in[7:6]};
3'b111: value_out = {value_in[6:0], value_in[7]};
endcase
3'b1_00: value_out = value_in << length;
3'b1_01: value_out = {value_in[7], value_in[6:0] << length};
3'b1_10: case(length)
3'b000: value_out = value_in;
3'b001: value_out = {value_in[6:0], value_in[7]};
3'b010: value_out = {value_in[5:0], value_in[7:6]};
3'b011: value_out = {value_in[4:0], value_in[7:5]};
3'b100: value_out = {value_in[3:0], value_in[7:4]};
3'b101: value_out = {value_in[2:0], value_in[7:3]};
3'b110: value_out = {value_in[1:0], value_in[7:2]};
3'b111: value_out = {value_in[0], value_in[7:1]};
endcase
default: value_out = value_in;
endcase
end
assign result = value_out;
endmodule
module testbench;
reg clk, direction;
reg [1:0] type;
reg [2:0] length;
reg [7:0] value_in;
wire [7:0] result;
shifter shifter1(result, value_in, direction, type, length);
initial begin
clk = 0;
direction = 1; type = 1; length = 3; value_in = 'b11110110;
$display("direction = %d type = %d length = %d value_in = %b",
direction, type, length, value_in);
#10 $display("done");
$finish;
end
always #5 clk = !clk;
always @(posedge clk) $strobe("result: %b", result);
endmodule |
Request for Answer Clarification by
motts786-ga
on
11 May 2005 14:48 PDT
There are no multiplexers used in the design, as it specifies in the specs?
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:07 PDT
Hi
This is behavioral code, the case statements turn into a mux.
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:08 PDT
Testing.
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:15 PDT
Testing post.
|
Request for Answer Clarification by
motts786-ga
on
11 May 2005 15:21 PDT
could you use the test bench provided:
module test_Shifter_8;
reg [7:0] val;
reg dir;
reg [1:0] type;
reg [2:0] len;
wire [7:0] shifted_S;
wire [7:0] shifted_B;
integer m, l, k, j, Total_errors;
reg error;
/*
Module "test_Shifter_8" reports results of shifting a value with
"shifter_8_Struct" and "shifter_8_Behav" and presents
differences in results as errors. Two useful modifications to this
test module are:
(1) Reduce the "Stopwatch" delay value to shorten run time. (#12500
accommodates the exhaustive case.)
(2) Adjust the initial_statement and control_expression of the "m"
for loop to run specific cases. (m= 0; m<=255; m=m+1)
results in the exhaustive case.
It may be necessary to disable the "Save all sim data" option on the
"Project Settings ..." menu of the "Project" pull-down
list to reduce the amount of data saved to disk.
*/
// Stopwatch
initial #12500 $finish;
//
initial begin
Total_errors = 0;
for (m= 0; m<=255; m=m+1) begin
val = m;
for (l=0; l<=7; l=l+1) begin
len = l;
for (k=0; k<=1;k=k+1) begin
dir = k;
for (j=0; j<=2; j=j+1) begin
type = j;
error = 0;
#1 if (shifted_S != shifted_B) begin
error = 1;
Total_errors = Total_errors + 1;
end
$display ("T = %3d, Dir = %b, Type = %b, Length = %b, Val =
%b , Res_S = %b, Res_B = %b, Err = %b, Tot err = %2d",
$time, dir, type, len, val, shifted_S, shifted_B, error, Total_errors);
end
end
end
end
$display ("T = %5d, The total numer of errors is: %5d", $time, Total_errors);
end
// Instances of two Shifter modules
shifter_8_Struct Shift1 (shifted_S, val, dir, type, len);
shifter_8_Behav Shift2 (shifted_B, val, dir, type, len);
endmodule
|
Request for Answer Clarification by
motts786-ga
on
11 May 2005 15:22 PDT
THis is what i get when i try to simulate
S I L O S Version 2001.120
DEMO COPY LIMITED TO 200 DEVICES AND 350 LINES OF HDL CODE
Copyright (c) 2001 by SIMUCAD Inc. All rights reserved.
No part of this program may be reproduced, transmitted,
transcribed, or stored in a retrieval system, in any
form or by any means without the prior written consent of
SIMUCAD Inc., 32970 Alvarado-Niles Road, Union City,
California, 94587, U.S.A.
(510)-487-9700 Fax: (510)-487-9721
Electronic Mail Address: "silos@simucad.com"
!file .sav="lab2"
!control .sav=3
!control .enablecache
!control .savcell=0
!control .disk=1000M
Reading "shifter_8_behav.v"
Reading "shifter_8_struct.v"
Reading "testbench.v"
sim to 0
Highest level modules (that have been auto-instantiated):
test_Shifter_8
error 3.089 : macro/module 'one_four_demux' has not been defined.
shifter_8_Behav
error 2.188 : errors are too severe to simulate
Ready: sim
error 2.188 : errors are too severe to simulate
Ready:
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:31 PDT
Hi,
I'm not sure you're taking my code...
I didn't have a any mux.
Who wrote:shifter_8_Behav.v?
Dod you name the modules correctly? Post all files and waveforms here.
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:34 PDT
Please understand everything in your testbench. Apprarently you mess up here:
shifter_8_Struct Shift1 (shifted_S, val, dir, type, len);
shifter_8_Behav Shift2 (shifted_B, val, dir, type, len);
Who wrote shifter_8_struct?
Who wrote shifter_8__behav?
Did you switch the two?
Can you post the structural code?
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:35 PDT
Most importantly, did you wrote the strucral code? :)
I hope you did. It's important that you do.
|
Request for Answer Clarification by
motts786-ga
on
11 May 2005 15:37 PDT
you wrote the behavioral, since i dont have the structural, i just
made another copy of your behavioral and renamed it to
shifter_8_struct, and your behavioral one to shifter_8_behav
|
Request for Answer Clarification by
motts786-ga
on
11 May 2005 15:37 PDT
I cant test just one they both have to be present it seems
|
Request for Answer Clarification by
motts786-ga
on
11 May 2005 15:38 PDT
I am not going to bother with the structural version, i just want to
obtain the expected output from his test bench for your behavioral
code
|
Request for Answer Clarification by
motts786-ga
on
11 May 2005 15:43 PDT
I did not write the structural version, I do not think i can get the
deadline extended, so I can only turn in half of the requirements. But
I need the output from this half for the report.
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:45 PDT
Hi,
Your approach is correct but what you mentioned above doesn't make sense--
the running is complaining about a one_four_demux--
there's no one_four_demux in my code, if you use my code for both behv
and structural, then there's no one_four_demux, right?
Apparently something else is in one of the files, not my code.
|
Request for Answer Clarification by
motts786-ga
on
11 May 2005 15:45 PDT
i was up all night trying to get the lfsr tb to work properly with ic
varying and tap constant. <----- BTW it works! :)
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:46 PDT
That's great! Good for you! Be sure to get some rest!
|
Request for Answer Clarification by
motts786-ga
on
11 May 2005 15:53 PDT
And you were right, I grouped the wrong files(they had the same name
from my previous work) into the project. Thank you.
|
Clarification of Answer by
studboy-ga
on
11 May 2005 15:59 PDT
You're welcomed. Hope it works. Thanks.
|