I need a Verilog behavioral model (verilog behavioral code) for a
floating point multiplier.

Have a look through this general search to see if it has what you want:

://www.google.co.uk/search?sourceid=navclient&ie=UTF-8&rls=GGLG,GGLG:2005-43,GGLG:en&q=verilog+behavioral+code+for+floating+point+multiplier

Alternatively, this might be just what you want:

http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/2.0/AMS-LRM-2-0.pdf

If this answers your question, donate the fee to the American Hurricane Appeal!

//-------------------------------------------------------
//
// Thi module takes in two floating point numbers as
// expressed by their characteristics and mantissas
// and return the result of their multiplication in
// in the same format.
//
// For example, let us say we want to multiply x1 = 1.2
// by x2 = 3.4. In this case, x1 can be representted as
// 12*(10^-1). So we assign
// x1_characteristic = 12 and x1_mantissa = -1
// Similarly, we can represent
// x2_characteristic = 34 and x2_mantissa = -1
// The result of the multiplication is
// (x1_characteristic*x2_characteristic)*(10^(x1_mantissa+x2_mantissa))
// = (12*34) * (10^(-1-1))
// = 408*10^(-2)
// The output is calculated as
// y_characteristic = 408 and y_mantissa = -2.
//
// The module is limited by the width of its inputs. But
// you can parameterize that.
//-------------------------------------------------------

module float_mult (
     input             clk
   , input             reset

   , input wire [31:0] x1_characteristic
   , input wire [31:0] x1_mantissa
   , input wire [31:0] x2_characteristic
   , input wire [31:0] x2_mantissa

   , output reg [63:0] y_characteristic
   , output reg [32:0] y_mantissa
);

   reg [63:0] y_next_characteristic;
   reg [32:0] y_next_mantissa;

   always @(posedge clk) begin // { change it to 'negedge' if necessary
      if (reset) // active high reset, change it to ~reset if necessary
         {y_characteristic, y_mantissa} <= 0;
      else
         {y_characteristic, y_mantissa} <= {y_next_characteristic,
y_next_mantissa};
   end // }

   always @* begin // {
      y_next_characteristic = x1_characteristic * x2_characteristic;
      y_next_mantissa = x1_mantissa + x2_mantissa;
   end // }
endmodule