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Q: Verilog ALU design, shift operation error ( No Answer,   0 Comments )
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 Subject: Verilog ALU design, shift operation error Category: Computers > Programming Asked by: ohaqqi-ga List Price: \$10.00 Posted: 18 Oct 2006 09:04 PDT Expires: 18 Oct 2006 09:13 PDT Question ID: 774693
 ```I'm working on a small 16bit alu. My code is below. I keep getting these errors: ** Error: alu16.v(68): near "<<": syntax error ** Error: alu16.v(69): near "<<": syntax error ** Error: alu16.v(70): near "<<": expecting: IDENT ** Error: alu16.v(71): near "<<": expecting: IDENT and a bunch more IDENT errors. What is the syntax error, how do I correct this code? Compiling in Modelsim. Any other tips would be great, I will probably have more Questions after this is answered. **************** module alu16(A,B,C,alu_code,overflow); /**************************************************** 16 bit arithmetic logic unit parameter: A.........16-bit A input B.........16-bit B input alu_code..5-bit operation to perform C.........16-bit bit result output overflow..overflow status (used for signed operations) ****************************************************/ input [15:0] A,B; input [4:0] alu_code; output [15:0] C; output overflow; //internal nodes wire [15:0] A,B; reg [15:0] C; reg overflow; always @ (A or B or alu_code) begin //ARITHMETIC OPERATIONS if(alu_code[4:3] == 2'b00) begin case (alu_code[2:0]) 3'b000:C = !((!A + 1) + (!B + 1) + 1); //signed 2's complement addition 3'b001:C = A + B; 3'b010:C = !((!A + 1) - (!B + 1) + 1); //signed 2's complement subtraction 3'b011:C = A - B; 3'b100:C = A + 1; 3'b101:C = A - 1; default:C = 8'bx; endcase overflow = C[15]^C[14]; end //LOGIC OPERATIONS else if(alu_code[4:3] == 2'b01) begin case (alu_code[2:0]) 3'b000:C = A && B; 3'b001:C = A || B; 3'b010:C = ((!A)&&(B) || (A)&&(!B)); 3'b000:C = !A; default:C = 8'bx; endcase end //SHIFT OPERATIONS (<< >> are logical shifts, <<< >>> are arithmetic shifts in Verilog2001 and SystemVerilog) else if (alu_code[4:3] == 2'b10) begin case (alu_code[2:0]) 3'b000: if(B[3:0] == 4'b0000) A << 0; else if(B[3:0] == 4'b0001) A << 1; else if(B[3:0] == 4'b0010) A << 2; else if(B[3:0] == 4'b0011) A << 3; else if(B[3:0] == 4'b0100) A << 4; else if(B[3:0] == 4'b0101) A << 5; else if(B[3:0] == 4'b0110) A << 6; else if(B[3:0] == 4'b0111) A << 7; else if(B[3:0] == 4'b1000) A << 8; else if(B[3:0] == 4'b1001) A << 9; else if(B[3:0] == 4'b1010) A << 10; else if(B[3:0] == 4'b1011) A << 11; else if(B[3:0] == 4'b1100) A << 12; else if(B[3:0] == 4'b1101) A << 13; else if(B[3:0] == 4'b1110) A << 14; else if(B[3:0] == 4'b1111) A << 15; 3'b001: if(B[3:0] == 4'b0000) A >> 0; else if(B[3:0] == 4'b0001) A >> 1; else if(B[3:0] == 4'b0010) A >> 2; else if(B[3:0] == 4'b0011) A >> 3; else if(B[3:0] == 4'b0100) A >> 4; else if(B[3:0] == 4'b0101) A >> 5; else if(B[3:0] == 4'b0110) A >> 6; else if(B[3:0] == 4'b0111) A >> 7; else if(B[3:0] == 4'b1000) A >> 8; else if(B[3:0] == 4'b1001) A >> 9; else if(B[3:0] == 4'b1010) A >> 10; else if(B[3:0] == 4'b1011) A >> 11; else if(B[3:0] == 4'b1100) A >> 12; else if(B[3:0] == 4'b1101) A >> 13; else if(B[3:0] == 4'b1110) A >> 14; else if(B[3:0] == 4'b1111) A >> 15; 3'b010: if(B[3:0] == 4'b0000) A <<< 0; else if(B[3:0] == 4'b0001) A <<< 1; else if(B[3:0] == 4'b0010) A <<< 2; else if(B[3:0] == 4'b0011) A <<< 3; else if(B[3:0] == 4'b0100) A <<< 4; else if(B[3:0] == 4'b0101) A <<< 5; else if(B[3:0] == 4'b0110) A <<< 6; else if(B[3:0] == 4'b0111) A <<< 7; else if(B[3:0] == 4'b1000) A <<< 8; else if(B[3:0] == 4'b1001) A <<< 9; else if(B[3:0] == 4'b1010) A <<< 10; else if(B[3:0] == 4'b1011) A <<< 11; else if(B[3:0] == 4'b1100) A <<< 12; else if(B[3:0] == 4'b1101) A <<< 13; else if(B[3:0] == 4'b1110) A <<< 14; else if(B[3:0] == 4'b1111) A <<< 15; 3'b000: if(B[3:0] == 4'b0000) A >>> 0; else if(B[3:0] == 4'b0001) A >>> 1; else if(B[3:0] == 4'b0010) A >>> 2; else if(B[3:0] == 4'b0011) A >>> 3; else if(B[3:0] == 4'b0100) A >>> 4; else if(B[3:0] == 4'b0101) A >>> 5; else if(B[3:0] == 4'b0110) A >>> 6; else if(B[3:0] == 4'b0111) A >>> 7; else if(B[3:0] == 4'b1000) A >>> 8; else if(B[3:0] == 4'b1001) A >>> 9; else if(B[3:0] == 4'b1010) A >>> 10; else if(B[3:0] == 4'b1011) A >>> 11; else if(B[3:0] == 4'b1100) A >>> 12; else if(B[3:0] == 4'b1101) A >>> 13; else if(B[3:0] == 4'b1110) A >>> 14; else if(B[3:0] == 4'b1111) A >>> 15; endcase end end //SET CONDITION OPERATIONS endmodule```