I get these two errors for the declaration ---> reg [15:0] A,B;
** Error: alu16.v(31): Port mode is incompatible with declaration: A
** Error: alu16.v(31): Port mode is incompatible with declaration: B
here is the code. any more help on the ALU for a fee will be great.
****************
module alu16(A,B,C,alu_code,overflow);
/****************************************************
16 bit arithmetic logic unit
parameter:
A.........16-bit A bidirectional
B.........16-bit B input
alu_code..5-bit operation to perform
C.........16-bit bit result output
overflow..overflow status (used for signed operations)
****************************************************/
inout [15:0] A;
inout [15:0] B;
input [4:0] alu_code;
output [15:0] C;
output overflow;
//internal nodes
reg [15:0] A,B;
reg [15:0] C;
reg overflow;
always @ (A or B or alu_code) begin
//ARITHMETIC OPERATIONS
if(alu_code[4:3] == 2'b00) begin
case (alu_code[2:0])
3'b000:C = !((!A + 1) + (!B + 1) + 1); //signed 2's complement addition
3'b001:C = A + B;
3'b010:C = !((!A + 1) - (!B + 1) + 1); //signed 2's complement subtraction
3'b011:C = A - B;
3'b100:C = A + 1;
3'b101:C = A - 1;
default:C = 8'bx;
endcase
overflow = C[15]^C[14];
end
//LOGIC OPERATIONS
else if(alu_code[4:3] == 2'b01) begin
case (alu_code[2:0])
3'b000:C = A && B;
3'b001:C = A || B;
3'b010:C = ((!A)&&(B) || (A)&&(!B));
3'b000:C = !A;
default:C = 8'bx;
endcase
end
//SHIFT OPERATIONS (<< >> are logical shifts, <<< >>> are arithmetic
shifts in Verilog2001 and SystemVerilog)
else if (alu_code[4:3] == 2'b10) begin
case (alu_code[2:0])
3'b000:
if(B[3:0] == 4'b0000) A = A << 0;
else if(B[3:0] == 4'b0001) A = A << 1;
else if(B[3:0] == 4'b0010) A = A << 2;
else if(B[3:0] == 4'b0011) A = A << 3;
else if(B[3:0] == 4'b0100) A = A << 4;
else if(B[3:0] == 4'b0101) A = A << 5;
else if(B[3:0] == 4'b0110) A = A << 6;
else if(B[3:0] == 4'b0111) A = A << 7;
else if(B[3:0] == 4'b1000) A = A << 8;
else if(B[3:0] == 4'b1001) A = A << 9;
else if(B[3:0] == 4'b1010) A = A << 10;
else if(B[3:0] == 4'b1011) A = A << 11;
else if(B[3:0] == 4'b1100) A = A << 12;
else if(B[3:0] == 4'b1101) A = A << 13;
else if(B[3:0] == 4'b1110) A = A << 14;
else if(B[3:0] == 4'b1111) A = A << 15;
3'b001:
if(B[3:0] == 4'b0000) A = A >> 0;
else if(B[3:0] == 4'b0001) A = A >> 1;
else if(B[3:0] == 4'b0010) A = A >> 2;
else if(B[3:0] == 4'b0011) A = A >> 3;
else if(B[3:0] == 4'b0100) A = A >> 4;
else if(B[3:0] == 4'b0101) A = A >> 5;
else if(B[3:0] == 4'b0110) A = A >> 6;
else if(B[3:0] == 4'b0111) A = A >> 7;
else if(B[3:0] == 4'b1000) A = A >> 8;
else if(B[3:0] == 4'b1001) A = A >> 9;
else if(B[3:0] == 4'b1010) A = A >> 10;
else if(B[3:0] == 4'b1011) A = A >> 11;
else if(B[3:0] == 4'b1100) A = A >> 12;
else if(B[3:0] == 4'b1101) A = A >> 13;
else if(B[3:0] == 4'b1110) A = A >> 14;
else if(B[3:0] == 4'b1111) A = A >> 15;
3'b010:
if(B[3:0] == 4'b0000) A = A <<< 0;
else if(B[3:0] == 4'b0001) A = A <<< 1;
else if(B[3:0] == 4'b0010) A = A <<< 2;
else if(B[3:0] == 4'b0011) A = A <<< 3;
else if(B[3:0] == 4'b0100) A = A <<< 4;
else if(B[3:0] == 4'b0101) A = A <<< 5;
else if(B[3:0] == 4'b0110) A = A <<< 6;
else if(B[3:0] == 4'b0111) A = A <<< 7;
else if(B[3:0] == 4'b1000) A = A <<< 8;
else if(B[3:0] == 4'b1001) A = A <<< 9;
else if(B[3:0] == 4'b1010) A = A <<< 10;
else if(B[3:0] == 4'b1011) A = A <<< 11;
else if(B[3:0] == 4'b1100) A = A <<< 12;
else if(B[3:0] == 4'b1101) A = A <<< 13;
else if(B[3:0] == 4'b1110) A = A <<< 14;
else if(B[3:0] == 4'b1111) A = A <<< 15;
3'b000:
if(B[3:0] == 4'b0000) A = A >>> 0;
else if(B[3:0] == 4'b0001) A = A >>> 1;
else if(B[3:0] == 4'b0010) A = A >>> 2;
else if(B[3:0] == 4'b0011) A = A >>> 3;
else if(B[3:0] == 4'b0100) A = A >>> 4;
else if(B[3:0] == 4'b0101) A = A >>> 5;
else if(B[3:0] == 4'b0110) A = A >>> 6;
else if(B[3:0] == 4'b0111) A = A >>> 7;
else if(B[3:0] == 4'b1000) A = A >>> 8;
else if(B[3:0] == 4'b1001) A = A >>> 9;
else if(B[3:0] == 4'b1010) A = A >>> 10;
else if(B[3:0] == 4'b1011) A = A >>> 11;
else if(B[3:0] == 4'b1100) A = A >>> 12;
else if(B[3:0] == 4'b1101) A = A >>> 13;
else if(B[3:0] == 4'b1110) A = A >>> 14;
else if(B[3:0] == 4'b1111) A = A >>> 15;
endcase
end
end
//SET CONDITION OPERATIONS
endmodule |