I get an error port mode is incompatible with declaration A if I try
to set A = temp in the code below. How can I set A = temp (A must be
wire, temp is reg). If I set A to a reg, I get other compile time
errors:
/////////////////////////////////////////
module alu16(A,B,alu_code,C,overflow);

/****************************************************
16 bit arithmetic logic unit

parameter:
A.........16-bit A bidirectional
B.........16-bit B input
alu_code..5-bit operation to perform
C.........16-bit bit result output
overflow..overflow status (used for signed operations)
****************************************************/
	input [15:0] A;
	input [15:0] B;
	input [4:0] alu_code;
	output [15:0] C;
	output overflow;

//internal nodes

	reg [15:0] temp;
	wire [15:0] A,B;
	reg [15:0] C;
	reg overflow;
	
always @ (A or B or alu_code) begin

//ARITHMETIC OPERATIONS

if(alu_code[4:3] == 2'b00) begin
	case (alu_code[2:0])
		3'b000:C = !((!A + 1'b1) + (!B + 1'b1) + 1'b1);	//signed 2's complement addition
		3'b001:C = A + B;
		3'b010:C = !((!A + 1'b1) - (!B + 1'b1) + 1'b1);	//signed 2's
complement subtraction
		3'b011:C = A - B;
		3'b100:C = A + 1'b1;
		3'b101:C = A - 1'b1;
		default:C = 8'bx;
	endcase
		overflow = C[15]^C[14];
	end

//LOGIC OPERATIONS

else if(alu_code[4:3] == 2'b01) begin
	case (alu_code[2:0])
		3'b000:C = A && B;
		3'b001:C = A || B;
		3'b010:C = ((!A)&&(B) || (A)&&(!B)); //definition of XOR
		3'b000:C = !A;
		default:C = 8'bx;
	endcase
	end

//SHIFT OPERATIONS (<< >> are logical shifts, <<< >>> are arithmetic
shifts in Verilog2001 and SystemVerilog)

else if (alu_code[4:3] == 2'b10) begin
	case (alu_code[2:0])
		3'b000:
		if(B[3:0] == 4'b0001) temp = A << 1;
		else if(B[3:0] == 4'b0010) temp = A << 2;
		else if(B[3:0] == 4'b0011) temp = A << 3;
		else if(B[3:0] == 4'b0100) temp = A << 4;
		else if(B[3:0] == 4'b0101) temp = A << 5;
		else if(B[3:0] == 4'b0110) temp = A << 6;
		else if(B[3:0] == 4'b0111) temp = A << 7;
		else if(B[3:0] == 4'b1000) temp = A << 8;
		else if(B[3:0] == 4'b1001) temp = A << 9;
		else if(B[3:0] == 4'b1010) temp = A << 10;
		else if(B[3:0] == 4'b1011) temp = A << 11;
		else if(B[3:0] == 4'b1100) temp = A << 12;
		else if(B[3:0] == 4'b1101) temp = A << 13;
		else if(B[3:0] == 4'b1110) temp = A << 14;
		else if(B[3:0] == 4'b1111) temp = A << 15;
		3'b001:
		if(B[3:0] == 4'b0001) temp = A >> 1;
		else if(B[3:0] == 4'b0010) temp = A >> 2;
		else if(B[3:0] == 4'b0011) temp = A >> 3;
		else if(B[3:0] == 4'b0100) temp = A >> 4;
		else if(B[3:0] == 4'b0101) temp = A >> 5;
		else if(B[3:0] == 4'b0110) temp = A >> 6;
		else if(B[3:0] == 4'b0111) temp = A >> 7;
		else if(B[3:0] == 4'b1000) temp = A >> 8;
		else if(B[3:0] == 4'b1001) temp = A >> 9;
		else if(B[3:0] == 4'b1010) temp = A >> 10;
		else if(B[3:0] == 4'b1011) temp = A >> 11;
		else if(B[3:0] == 4'b1100) temp = A >> 12;
		else if(B[3:0] == 4'b1101) temp = A >> 13;
		else if(B[3:0] == 4'b1110) temp = A >> 14;
		else if(B[3:0] == 4'b1111) temp = A >> 15;
		3'b010:
		if(B[3:0] == 4'b0001) temp = A <<< 1;
		else if(B[3:0] == 4'b0010) temp = A <<< 2;
		else if(B[3:0] == 4'b0011) temp = A <<< 3;
		else if(B[3:0] == 4'b0100) temp = A <<< 4;
		else if(B[3:0] == 4'b0101) temp = A <<< 5;
		else if(B[3:0] == 4'b0110) temp = A <<< 6;
		else if(B[3:0] == 4'b0111) temp = A <<< 7;
		else if(B[3:0] == 4'b1000) temp = A <<< 8;
		else if(B[3:0] == 4'b1001) temp = A <<< 9;
		else if(B[3:0] == 4'b1010) temp = A <<< 10;
		else if(B[3:0] == 4'b1011) temp = A <<< 11;
		else if(B[3:0] == 4'b1100) temp = A <<< 12;
		else if(B[3:0] == 4'b1101) temp = A <<< 13;
		else if(B[3:0] == 4'b1110) temp = A <<< 14;
		else if(B[3:0] == 4'b1111) temp = A <<< 15;
		3'b000:
		if(B[3:0] == 4'b0001) temp = A >>> 1;
		else if(B[3:0] == 4'b0010) temp = A >>> 2;
		else if(B[3:0] == 4'b0011) temp = A >>> 3;
		else if(B[3:0] == 4'b0100) temp = A >>> 4;
		else if(B[3:0] == 4'b0101) temp = A >>> 5;
		else if(B[3:0] == 4'b0110) temp = A >>> 6;
		else if(B[3:0] == 4'b0111) temp = A >>> 7;
		else if(B[3:0] == 4'b1000) temp = A >>> 8;
		else if(B[3:0] == 4'b1001) temp = A >>> 9;
		else if(B[3:0] == 4'b1010) temp = A >>> 10;
		else if(B[3:0] == 4'b1011) temp = A >>> 11;
		else if(B[3:0] == 4'b1100) temp = A >>> 12;
		else if(B[3:0] == 4'b1101) temp = A >>> 13;
		else if(B[3:0] == 4'b1110) temp = A >>> 14;
		else if(B[3:0] == 4'b1111) temp = A >>> 15;
	endcase
	end
end

//SET CONDITION OPERATIONS
endmodule